The present invention relates in general to digital signal processor integrated circuits, and more specifically, to a processing architecture having reconfigurable blocks to minimize integrated circuit area required to process multi-band radio signals, such as AM and FM.
With the advent of high speed digital signal processing (DSP) components, radio receivers are being introduced using DSP integrated circuits to implement demodulation and various other functions in a radio receiver. In particular, it is becoming possible to digitally process the intermediate frequency (IF) signal or even the radio frequency (RF) signal, thus avoiding a large number of analog circuits and components with their associated costs and space requirements. In order to keep costs down for a particular audio system, DSP performance in terms of 1) chip area required for processing, and 2) execution time, each need to be minimized.
DSP components are typically organized into blocks, each block performing a particular function such as decimating, filtering, or signal detection. In a multi-band radio receiver, the exact functions which must be performed to reproduce each different type of broadcast may be significantly different. For example, AM and FM broadcast signals are transmitted using different types of modulation and different bandwidths. Consequently, separate chains of processing blocks have been used in prior art DSP components to separately process AM and FM signals. This inefficient use of DSP chip area results in higher costs both for the DSP integrated circuits themselves and the audio systems which use them.